1. Field of the Invention
The present invention relates to a voltage translator capable of switching a supply voltage at a high speed in a semiconductor integrated circuit.
2. Related Art
There is a case where a plurality of voltages having different values are used inside the semiconductor integrated circuit. In case of a currently available flash electrically erasable and programmable read-only memory (flash EEPROM), for instance, the voltage of about 5V is applied to a word line selected to read the data therefrom while the other word lines not selected are made to be at the ground (earth) potential. On one hand, in the other logical circuits like a decoder and so forth, the voltage of about 3V is used as a power source voltage. Here, the above voltage values are not definitive but only illustrative, and would be variable depending on the future improvement and development of the semiconductor manufacturing process.
In order to execute the high speed data read, it is required to speedily vary the word line voltage in response to the selection signal of the word line. A circuit having the function capable of meeting this requirement is called a xe2x80x9cVoltage Translator.xe2x80x9d One of circuits of this kind has been disclosed by the Japanese Patent Publication No. 10-149693. FIG. 9 of the drawings attached hereto shows the circuit diagram of the prior art voltage translator 90 disclosed by the above patent publication. The voltage translator 90 is arranged such that the word line is connected, on one hand, with the earth VSS through the first NMOS type switching transistor N1 while it is connected, on the other hand, with an operation power source VX through the first PMOS type switching transistor P1. Furthermore, this voltage translator 90 includes the first PMOS type feedback transistor P2 put in such a state that it is directly driven by the voltage level of the word line, and the second NMOS type feedback transistor N2-r put in such a state that it is directly driven by the voltage level of the word line. In the circuit arrangement like this, the turn-on of the first NMOS type switching transistor N1 and the turn-off of the first PMOS type switching transistor P1 are accelerated by making use of the on/off of the second NMOS type feedback transistor N2-r, thereby realizing the high speed changeover of the word line voltage.
Each gate of transistors N1, N2-r, N3-r, P1, and P2 as shown in FIG. 9 has an equal gate length of 1.4 xcexcm while each gate of the same has correspondingly the gate width of 50 xcexcm, 6 xcexcm, 20 xcexcm, 40 xcexcm, and 4 xcexcm. Each gate of the PMOS type transistor and the NMOS transistor which constitute a decoder NOR and also an inverter INV-r, has the gate width of 15 xcexcm and 3 xcexcm in case of the decoder NOR while 10 xcexcm and 3 xcexcm in case of the inverter INV-r. In FIG. 9, a plurality of actual word lines are represented in a lump by a word line model illustrated in the form of a rectangular box (WL) by taking account of their floating capacity and others.
It takes 7 ns or so to apply the high voltage adopted by the circuit disclosed in the above patent publication to the selected word line, so that the process of increasing the voltage of the selected word line can be carried out at a high speed. On one hand, however, it takes 10 ns or so to reduce the high voltage applied to the selected word line to the lower voltage, so that the process of reducing the voltage applied to the selected word line is carried out at a slower speed, comparing with the above process of increasing the voltage of the selected word line.
If a plurality of such prior art voltage translators as describe above are used for the word line driving circuit of a semiconductor memory device, it becomes necessary to avoid the duplicated selection of the word line.
Accordingly, as described in the above, the switching operation for memory selection can not help being restricted by the non-selection switching time.
Consequently, in order to realize a more speedy memory read operation, it has been desired to develop a voltage translator having a more speedy non-selection switching time characteristic. Therefore, the invention has been made for the purpose of providing a novel and improved voltage translator having such a desired characteristic as described above.
Accordingly, in order to achieve the above object, the invention provides a voltage translator capable of supplying the operation voltage or a low voltage to the word line based on a decode signal. This voltage translator is characterized in that it is provided with an inverter, the first, third and fourth NMOS type transistors, and the first, second and third PMOS type transistors.
The inverter generates a logical selection signal based on the decode signal.
The first NMOS type transistor (N1) is provided with a source electrode connected with the low voltage source, a drain electrode connected with the word line, and a gate electrode connected with the output terminal of the inverter.
The first PMOS type transistor (P1) is provided with a source electrode connected with the operation voltage source and a drain electrode connected with the word line.
The second PMOS type transistor (P2) is provided with a source electrode connected with the operation voltage source and a drain electrode connected with the gate of the first PMOS type transistor.
The third NMOS type transistor (N3) is provided with a source electrode connected with the gate electrode of the second PMOS type transistor, a drain electrode connected with the operation voltage source, and a gate electrode connected with the word line.
The third PMOS type transistor (P3) is provided with a source electrode connected with the gate electrode of the second PMOS type transistor and with the source electrode of the third NMOS transistor, a drain electrode connected with the word line, and a gate electrode connected with the gate electrode of the first PMOS type transistor.
The fourth NMOS type transistor (N4) is provided with a source electrode connected with the low voltage source, a drain electrode connected with the gate electrode of the second PMOS type transistor, and a gate electrode connected with the output terminal of the inverter.
The second PMOS type transistor functions as a feedback transistor in the voltage translator. With the circuit arrangement as described above, it becomes possible to drive the operation voltage by means of the logical control voltage. Still further, with this circuit arrangement, as the response of the feedback path transmitting the word line voltage to the gate electrode of the second PMOS type transistor is made faster, the voltage of the word line is speedily changed to the low voltage level in the switching process from the selection to the non-selection process, thereby the speedy non-selection switching becoming possible. As a result, the voltage of the word line can be speedily reduced to the low voltage level.
Some preferred embodiments of the invention will now be described in detail in the following, with reference to the accompanying drawings. The numerical values as used for expressing time, length, width and so forth in the following description are not definitive but illustrative to the last.